Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Cocotb | 1,583 | 9 | 22 | 25 days ago | 44 | October 06, 2023 | 415 | bsd-3-clause | Python | |
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python | ||||||||||
Chiselverify | 114 | 7 months ago | 3 | October 10, 2022 | 4 | bsd-2-clause | Scala | |||
A dynamic verification library for Chisel. | ||||||||||
Ivtest | 95 | 2 years ago | gpl-2.0 | Verilog | ||||||
Regression test suite for Icarus Verilog. (OBSOLETE) | ||||||||||
Kansas Lava | 42 | 5 years ago | 5 | April 06, 2018 | 16 | other | Haskell | |||
Kansas Lava | ||||||||||
Dram Bender | 21 | 7 months ago | 1 | mit | VHDL | |||||
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf | ||||||||||
Libvhdl | 19 | 2 years ago | other | VHDL | ||||||
Library of reusable VHDL components | ||||||||||
Oram_fpga | 8 | 9 years ago | 2 | VHDL | ||||||
FPGA related files for ORAM | ||||||||||
Vhdeps | 8 | 4 years ago | 12 | October 25, 2019 | 7 | apache-2.0 | VHDL | |||
VHDL dependency analyzer | ||||||||||
Backplane | 6 | 14 years ago | VHDL | |||||||
Soma Backplane Hardware | ||||||||||
Lzw_verilog | 5 | 10 years ago | VHDL | |||||||
LZW Compressoion algorithm in verilog |