Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
---|---|---|---|---|---|---|---|---|---|---|
Awesome Electronics | 4,754 | 3 months ago | 18 | cc0-1.0 | ||||||
A curated list of awesome resources for electronic engineers and hobbyists | ||||||||||
Skidl | 889 | 19 days ago | 3 | October 23, 2021 | 37 | mit | Python | |||
SKiDL is a module that extends Python with the ability to design electronic circuits. | ||||||||||
Haxo Hw | 485 | 3 months ago | 2 | other | XSLT | |||||
Haxophone, an electronic musical instrument that resembles a saxophone | ||||||||||
Kicad_footprints | 287 | 4 months ago | 4 | mit | Python | |||||
A collection of all the KiCad footprints on the internet | ||||||||||
8bit Cpu | 253 | a year ago | mit | Python | ||||||
Schematics & code for my 74LS-based 8-bit MK1 CPU | ||||||||||
Kitspace | 234 | 5 days ago | 59 | other | JavaScript | |||||
A place to share electronics projects | ||||||||||
Rp2040 Motor Controller | 233 | 3 days ago | 5 | other | HTML | |||||
A dual channel brushless motor controller based on the RP2040 microcontroller, designed in Kicad. | ||||||||||
Ethersweep | 190 | 4 days ago | 5 | other | C++ | |||||
Open Source, easy to use Ethernet connected stepper motor controller. Built in FreeCAD, KiCAD and Arduino. | ||||||||||
Piantor | 161 | 2 months ago | 2 | gpl-3.0 | ||||||
The Piantor Keyboard is a beginner-friendly, easy-to-solder, 42-key or 36-key, diodeless, low profile aggressive column staggered, hotswappable and non-hotswappable, programmable ergonomic mechanical split keyboard powered by Raspberry Pi Pico or other compatible RP2040 boards. It is based on the Cantor Keyboard. | ||||||||||
Goldfish | 160 | 10 months ago | ||||||||
A small, thin, USB-C, Pro Micro compatible microcontroller |
The SKiDL Python package lets you compactly describe the interconnection of electronic circuits and components. The resulting Python program performs electrical rules checking for common mistakes and outputs a netlist that serves as input to a PCB layout tool.
diff
and git for circuits).As a very simple example (see more in the blog), the SKiDL program below describes a two-input AND gate built from discrete transistors:
from skidl import *
# Create part templates.
q = Part("Device", "Q_PNP_CBE", dest=TEMPLATE)
r = Part("Device", "R", dest=TEMPLATE)
# Create nets.
gnd, vcc = Net("GND"), Net("VCC")
a, b, a_and_b = Net("A"), Net("B"), Net("A_AND_B")
# Instantiate parts.
gndt = Part("power", "GND") # Ground terminal.
vcct = Part("power", "VCC") # Power terminal.
q1, q2 = q(2) # Two transistors.
r1, r2, r3, r4, r5 = r(5, value="10K") # Five 10K resistors.
# Make connections between parts.
a & r1 & q1["B C"] & r4 & q2["B C"] & a_and_b & r5 & gnd
b & r2 & q1["B"]
q1["C"] & r3 & gnd
vcc += q1["E"], q2["E"], vcct
gnd += gndt
generate_netlist()
And this is the output that can be fed to a program like KiCad's PCBNEW
to
create the physical PCB:
(export (version D) (design (source "/media/devb/Main/devbisme/KiCad/tools/skidl/skidl/circuit.py") (date "05/11/2021 10:40 AM") (tool "SKiDL (1.0.0)")) (components (comp (ref #PWR1) (value GND) (footprint "No Footprint") (fields (field (name F0) #PWR) (field (name F1) GND)) (libsource (lib power) (part GND)) (sheetpath (names /top/16948080335112909674) (tstamps /top/16948080335112909674))) (comp (ref #PWR2) (value VCC) (footprint "No Footprint") (fields (field (name F0) #PWR) (field (name F1) VCC)) (libsource (lib power) (part VCC)) (sheetpath (names /top/10777333099431236833) (tstamps /top/10777333099431236833))) (comp (ref Q1) (value Q_PNP_CBE) (footprint "No Footprint") (fields (field (name F0) Q) (field (name F1) Q_PNP_CBE)) (libsource (lib Device) (part Q_PNP_CBE)) (sheetpath (names /top/5605641708446153824) (tstamps /top/5605641708446153824))) (comp (ref Q2) (value Q_PNP_CBE) (footprint "No Footprint") (fields (field (name F0) Q) (field (name F1) Q_PNP_CBE)) (libsource (lib Device) (part Q_PNP_CBE)) (sheetpath (names /top/3991298653620578089) (tstamps /top/3991298653620578089))) (comp (ref R1) (value 10K) (footprint "No Footprint") (fields (field (name F0) R) (field (name F1) R)) (libsource (lib Device) (part R)) (sheetpath (names /top/17650585640079795295) (tstamps /top/17650585640079795295))) (comp (ref R2) (value 10K) (footprint "No Footprint") (fields (field (name F0) R) (field (name F1) R)) (libsource (lib Device) (part R)) (sheetpath (names /top/11461493733231665754) (tstamps /top/11461493733231665754))) (comp (ref R3) (value 10K) (footprint "No Footprint") (fields (field (name F0) R) (field (name F1) R)) (libsource (lib Device) (part R)) (sheetpath (names /top/1249286041592970488) (tstamps /top/1249286041592970488))) (comp (ref R4) (value 10K) (footprint "No Footprint") (fields (field (name F0) R) (field (name F1) R)) (libsource (lib Device) (part R)) (sheetpath (names /top/7242640812520981502) (tstamps /top/7242640812520981502))) (comp (ref R5) (value 10K) (footprint "No Footprint") (fields (field (name F0) R) (field (name F1) R)) (libsource (lib Device) (part R)) (sheetpath (names /top/9932266607871614386) (tstamps /top/9932266607871614386)))) (nets (net (code 1) (name A) (node (ref R1) (pin 1))) (net (code 2) (name A_AND_B) (node (ref Q2) (pin 1)) (node (ref R5) (pin 1))) (net (code 3) (name B) (node (ref R2) (pin 1))) (net (code 4) (name GND) (node (ref #PWR1) (pin 1)) (node (ref R3) (pin 2)) (node (ref R5) (pin 2))) (net (code 5) (name N$1) (node (ref Q1) (pin 2)) (node (ref R1) (pin 2)) (node (ref R2) (pin 2))) (net (code 6) (name N$2) (node (ref Q1) (pin 1)) (node (ref R3) (pin 1)) (node (ref R4) (pin 1))) (net (code 7) (name N$3) (node (ref Q2) (pin 2)) (node (ref R4) (pin 2))) (net (code 8) (name VCC) (node (ref #PWR2) (pin 1)) (node (ref Q1) (pin 3)) (node (ref Q2) (pin 3)))) )