Digital Logic Design Lab Experiments S2023
Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Hw | 1,254 | 2 years ago | 193 | other | Verilog | |||||
| RTL, Cmodel, and testbench for NVDLA | ||||||||||
| Accdnn | 121 | 5 years ago | 2 | apache-2.0 | Verilog | |||||
| A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration. | ||||||||||
| Learning Nvdla Notes | 117 | 6 years ago | 17 | |||||||
| NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected] | ||||||||||
| Fpga_based_cnn | 113 | 7 years ago | 3 | Verilog | ||||||
| FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform. | ||||||||||
| Spatial Lang | 98 | 2 | 6 years ago | 1 | March 11, 2018 | 58 | mit | Verilog | ||
| Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language" | ||||||||||
| Tapasco | 87 | 8 months ago | 56 | lgpl-3.0 | Verilog | |||||
| The Task Parallel System Composer (TaPaSCo) | ||||||||||
| Skrskr | 76 | 2 years ago | 4 | other | Tcl | |||||
| The second place winner for DAC-SDC 2020 | ||||||||||
| Clacc | 51 | 7 years ago | mit | Verilog | ||||||
| Deep Learning Accelerator (Convolution Neural Networks) | ||||||||||
| Cnn Accelerator Vlsi | 48 | a year ago | 1 | apache-2.0 | Verilog | |||||
| Convolutional accelerator kernel, target ASIC & FPGA | ||||||||||
| Marlann | 46 | 5 years ago | Verilog | |||||||
| Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks | ||||||||||
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