Ice Risc
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Icestudio | 1,621 | 4 months ago | 117 | gpl-2.0 | JavaScript | |||||
| :snowflake: Visual editor for open FPGA boards | ||||||||||
| Apio | 671 | 1 | 7 months ago | 144 | October 03, 2023 | 26 | gpl-2.0 | Verilog | ||
| :seedling: Open source ecosystem for open FPGA boards | ||||||||||
| Ice40 Playground | 224 | 9 months ago | 2 | other | Verilog | |||||
| Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker) | ||||||||||
| Ice40_ultraplus_examples | 115 | 2 years ago | 3 | mpl-2.0 | Verilog | |||||
| Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation | ||||||||||
| Icestation 32 | 107 | 3 years ago | 2 | mit | Verilog | |||||
| Compact FPGA game console | ||||||||||
| Ice40 | 75 | 6 years ago | Verilog | |||||||
| Lattice iCE40 FPGA experiments - Work in progress | ||||||||||
| Ponylink | 63 | 8 years ago | Verilog | |||||||
| A single-wire bi-directional chip-to-chip interface for FPGAs | ||||||||||
| Icez0mb1e | 49 | a year ago | 3 | mit | Verilog | |||||
| FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC | ||||||||||
| Iua | 35 | 4 years ago | Verilog | |||||||
| ice40 USB Analyzer | ||||||||||
| Beaglewire | 32 | 6 years ago | 9 | gpl-2.0 | Verilog | |||||
| This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017 | ||||||||||
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