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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SystemVerilog to Verilog conversion

Verilog Mode ⭐ 231

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Clarvi simple RISC-V processor for teaching

Netlist Paths ⭐ 19

A library and command-line tool for querying a Verilog netlist.

Virtio implementation in SystemVerilog

Dragonphy2 ⭐ 17

Open Source PHY v2

SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity

Verilator_ext_tests ⭐ 12

Extended and external tests for Verilator testing

Uvm_tb_cross_bar ⭐ 11

SystemVerilog UVM testbench example

Mil1553 Spi ⭐ 8

MIL-STD-1553 <-> SPI bridge

A simple 5-stage Pipeline RISC-V core

CHIPKIT: An agile, reusable open-source framework for rapid test chip development

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