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Search results for spi risc v

9 search results found

Ice40_ultraplus_examples ⭐ 115

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Hydrausb3_fw ⭐ 48

HydraUSB3 (WCH CH569) open source test firmware / examples / libraries to experiment with streaming / high-speed protocols (USB2 HS, USB3 SS, HSPI, SerDes...)

Hydrausb3_hw ⭐ 26

HydraUSB3 V1 is an open source developer kit for the WCH CH569 MCU to experiment with streaming / high-speed protocols(USB2 HS, USB3 SS, HSPI, SerDes...)

Maixduino Genplus ⭐ 10

Genesis-Plus-GX based MEGADRIVE/GENESIS emulator for the Maixduino

Riscv_soc ⭐ 10

Basic RISC-V Test SoC

Wch Ch56x Bsp ⭐ 9

WCH CH56x BSP for HydraUSB3 v1 hardware

Up5k_riscv ⭐ 7

There are many RISC V projects on iCE40. This one is mine.

Lora Sx1262 ⭐ 7

LoRa Driver for Semtech SX1262 on Apache NuttX OS, Linux (PineDio USB Adapter) and BL602 IoT SDK (PineDio Stack BL604)

Renode Linux Runner Action ⭐ 5

Run your tests in a configurable, emulated Linux environment with a custom kernel and access to virtual peripherals

Riscv_sbc ⭐ 5

A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.

Fpga_test_soc ⭐ 5

A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)

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