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Search results for scala risc v
risc-v
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14 search results found
Xiangshan
⭐
4,180
Open-source high-performance RISC-V processor
Rocket Chip
⭐
2,988
Rocket Chip Generator
Riscv Boom
⭐
1,524
SonicBOOM: The Berkeley Out-of-Order Machine
Firesim
⭐
778
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
Riscv Mini
⭐
427
Simple RISC-V 3-stage Pipeline in Chisel
Dana
⭐
147
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Saxonsoc
⭐
133
SoC based on VexRiscv and ICE40 UP5K
Awesome Riscv
⭐
96
😎 A curated list of awesome RISC-V implementations
Chiselv
⭐
88
A RISC-V Core (RV32I) written in Chisel HDL
Yatcpu
⭐
61
Yet another toy CPU.
Riscv Sodor
⭐
56
educational microarchitectures for risc-v isa
Dl_accelerator
⭐
44
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
Riscv Fivestage
⭐
41
Marginally better than redstone
Fuxi
⭐
40
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Tree Core Cpu
⭐
29
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
Proteus
⭐
27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
Learn Rv32i Asap
⭐
25
A Simple As Possible RISCV-32I core with debug module.
Chiffre
⭐
25
A fault-injection framework using Chisel and FIRRTL
Kyogenrv
⭐
25
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Boom Template
⭐
23
A template for building new projects/platforms using the BOOM core.
Rift2core
⭐
21
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
Systemoncat
⭐
17
An SoC with multiple RISC-V IMA processors.
Quasar
⭐
13
Quasar 2.0: Chisel equivalent of SweRV-EL2
Riscv32 Cpu Chisel
⭐
12
Learning how to make RISC-V 32bit CPU with Chisel
Dirv
⭐
12
This is my first trial project for designing RISC-V in Chisel
Prospect
⭐
11
ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
Riscv Self
⭐
8
mini risc-v kernel by Chisel 3
Rocket Chip Rocc
⭐
8
This repo contains source files and code for a synthesizable RISC-V processor with support for custom instructions in a co-processor.
Aleph
⭐
7
Aleph is a single cycle processor that carries out one instruction in a single clock cycle
Bossa
⭐
6
BOOM's Simulation Accelerator.
Learn Rv32i Arty
⭐
6
A Simple As Possible RISCV-32I on Digilent Arty board
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