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An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter

mirror of https://git.elphel.com/Elphel/ezynq

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