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Openlane
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1,148
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Caravel
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223
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Caravel_mpw One
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130
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
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