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Xilinx Deep Learning IP

Dnn Accelerator ⭐ 45

A DNN Accelerator implemented with RTL.

Cnn_vhdl_generator ⭐ 18

AUTOMATIC VHDL GENERATION FOR CNN MODELS

Verilog Convolutional Neural Network on PYNQ

Em070_new Fpga Family For Cnn Architectures High Speed Soft Neuron Design ⭐ 10

Who doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project i

Pocket Cnn ⭐ 9

CNN-to-FPGA-framework for small CNN, written in VHDL and Python

Cnn For Modulation Recognition Based On Fpga ⭐ 9

Dcnn Accelerator ⭐ 5

Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.

Landmark Detection with CNN on FPGA including DPR

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