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Search results for chisel3

28 search results found

Xiangshan ⭐ 4,180

Open-source high-performance RISC-V processor

Chisel ⭐ 3,750

Chisel: A Modern Hardware Design Language

Diagrammer ⭐ 74

Provides dot visualizations of chisel/firrtl circuits

Lectures ⭐ 63

Lectures for the Agile Hardware Design course in Jupyter Notebooks

Yet another toy CPU.

Tree Core Ide ⭐ 56

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Riscv Sodor ⭐ 56

educational microarchitectures for risc-v isa

Dl_accelerator ⭐ 44

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

Hardposit Chisel3 ⭐ 26

Chisel library for Unum Type-III Posit Arithmetic

Kyogenrv ⭐ 25

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Fpu Wrappers ⭐ 24

Wrappers for open source FPU hardware implementations.

Rift2core ⭐ 21

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Systemoncat ⭐ 17

An SoC with multiple RISC-V IMA processors.

Chisel Things for OFDM

Quasar 2.0: Chisel equivalent of SweRV-EL2

A caravan equipped with API for creating bus protocols in Chisel with ease.

Riscv32 Cpu Chisel ⭐ 12

Learning how to make RISC-V 32bit CPU with Chisel

100daysofchisel ⭐ 8

100 Days of CHISEL inspired by 100DaysOfRTL

Pythia Hdl ⭐ 8

Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

A polyphonic synthesizer built on fpga and esp32

Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL

Aleph is a single cycle processor that carries out one instruction in a single clock cycle

Vector_muladd_accelerator ⭐ 7

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

PYNQ with Chisel and Rust

Chisel Bfm Tester ⭐ 7

BFM Tester for Chisel HDL

FPGA implementation of the eNodeB and gNB physical layers

Processing Element ⭐ 5

A configurable processing element for deep neural network accelerators

Processing Engine ⭐ 5

A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.

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1-28 of 28 search results

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