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Search results for c plus plus eda
c-plus-plus
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eda
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15 search results found
Openroad
⭐
1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Opentimer
⭐
368
A High-performance Timing Analysis Tool for VLSI Systems
Gds2para
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76
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Cu Gr
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74
CUGR, VLSI Global Routing Tool Developed by CUHK
Gds3d
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61
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://githu
Fan_atpg
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51
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Ripple Fpga
⭐
47
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Fiction
⭐
45
An open-source design automation framework for Field-coupled Nanotechnologies
Naja
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34
Structural Netlist API (and more) for EDA post synthesis flow development
Coriolis
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28
Coriolis VLSI EDA Tool (LIP6)
Qt_painter
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22
CAD framework tool on top of Qt
Edaskel
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19
A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integration with the Qt event loop), a CMake build system, and a testing framework
Naja Verilog
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18
A standalone structural (gate-level) verilog parser
Imap
⭐
9
Logic optimization and technology mapping tool.
Chp2prs
⭐
6
Automated conversion from CHP to PRS using syntax-directed translation
Actsim
⭐
5
Simulator for ACT hardware description language
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