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Search results for c plus plus eda
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eda
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37 search results found
Librepcb
⭐
2,171
A powerful, innovative and intuitive EDA suite for everyone!
Kicad Source Mirror
⭐
1,571
This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.
Openroad
⭐
1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Vtr Verilog To Routing
⭐
925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Klayout
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663
KLayout Main Sources
Opentimer
⭐
368
A High-performance Timing Analysis Tool for VLSI Systems
Gdstk
⭐
278
Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.
Kactus2dev
⭐
168
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Limbo
⭐
117
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
Xictools
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116
XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
Dr Cu
⭐
97
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
Act
⭐
88
ACT hardware description language and core tools.
Repofibtori
⭐
87
🤓 Apunts, pràctiques, exàmens, enllaços i recursos actualitzats pel grau d'Enginyeria Informàtica de la FIB
Gds2para
⭐
76
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Cu Gr
⭐
74
CUGR, VLSI Global Routing Tool Developed by CUHK
Xplace
⭐
62
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
Gds3d
⭐
61
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://githu
Opendb
⭐
57
Database and Tool Framework for EDA
Fan_atpg
⭐
51
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Qtflow
⭐
47
Free open source EDA tools
Ripple Fpga
⭐
47
RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
Fiction
⭐
45
An open-source design automation framework for Field-coupled Nanotechnologies
Naja
⭐
34
Structural Netlist API (and more) for EDA post synthesis flow development
Parser Spef
⭐
29
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Ophidian
⭐
29
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Coriolis
⭐
28
Coriolis VLSI EDA Tool (LIP6)
Gerber2pdf
⭐
28
Gerber to PDF converter
Parser Verilog
⭐
24
A Standalone Structural Verilog Parser
Qt_painter
⭐
22
CAD framework tool on top of Qt
Nthu Route
⭐
21
VLSI EDA Global Router
Padring
⭐
19
A padring generator for ASICs
Edaskel
⭐
19
A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integration with the Qt event loop), a CMake build system, and a testing framework
Naja Verilog
⭐
18
A standalone structural (gate-level) verilog parser
Sv Jtracing_online
⭐
15
利用C++实现针对SystemVerilog的高性能在线编译系统,可将SystemVerilog源代 Syntax Tree,并提供Parser解析过程信息、报错信息和变量表,该在线编译系统通过webbenchh压力
Ciccreator
⭐
10
Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outputs a compiled layout file. The default output format is JSON, optionally GDS.
Salt
⭐
10
Steiner Shallow-Light Tree for VLSI Routing
Imap
⭐
9
Logic optimization and technology mapping tool.
Phi
⭐
7
Hardware description language that tries not to suck
Libcircuit
⭐
6
libCircuit is a C++ Library for EDA software development
Chp2prs
⭐
6
Automated conversion from CHP to PRS using syntax-directed translation
Actsim
⭐
5
Simulator for ACT hardware description language
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