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The Top 15 Verilog Vhdl Rtl Open Source Projects

Open source projects categorized as Verilog Vhdl Rtl
Categories > Hardware > Verilog
Categories > Hardware > Vhdl
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140most recent commit 3 months ago
Openwifi Hw ⭐ 560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
most recent commit 5 months ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34most recent commit 4 months agopypi hwt} Downloads
Spinalcrypto ⭐ 36
SpinalHDL - Cryptography libraries
most recent commit a year ago
Hwtlib ⭐ 33
hardware library for hwt (= ipcore repo)
total releases 28most recent commit 5 months ago
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11most recent commit 6 months agopypi hdlConvertorAst} Downloads
Design And Asic Implementation Of 32 Point Fft Processor ⭐ 20
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of a
most recent commit 5 months ago
Spinaldev ⭐ 12
Docker Development Environment for SpinalHDL
most recent commit 4 years ago
Digital Hardware Modelling ⭐ 11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
most recent commit 3 years ago
Rtl Coding ⭐ 6
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
most recent commit 8 months ago
Ruby_rtl ⭐ 5
Describing RTL circuit in Ruby
most recent commit 2 years ago
Lzw_verilog ⭐ 5
LZW Compressoion algorithm in verilog
most recent commit 10 years ago
Meowrouter Top ⭐ 5
Top for MeowRouter
most recent commit 4 years ago
The 3 Most Depended On Verilog Vhdl Rtl Open Source Projects
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140latest release November 01, 2023most recent commit 3 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
The 5 Latest Releases In Verilog Vhdl Rtl Open Source Projects
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140latest release November 01, 2023most recent commit 3 months ago
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Hwtlib ⭐ 33
hardware library for hwt (= ipcore repo)
total releases 28latest release July 02, 2021most recent commit 5 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
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