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The Top 23 Hardware Fpga Open Source Projects

Open source projects categorized as Hardware Fpga
Categories > Hardware > Fpga
Categories > Hardware > Hardware
Numerical Fpga Thesis ⭐ 28
Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH
most recent commit 9 years ago
Proteus ⭐ 27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
most recent commit 7 months ago
Cse548 Labs ⭐ 26
A repository containing homework labs for CSE548
most recent commit 7 years ago
Tenyr ⭐ 26
Simple, orthogonal 32-bit computer architecture and environment
total releases 1most recent commit a year ago
Uart ⭐ 25
A simple implementation of a UART modem in Verilog.
most recent commit 2 years ago
Quince ⭐ 24
a 2.4 GHz SDR neighbor using 1 bit ADC
most recent commit 2 years ago
Icebreaker Amaranth Examples ⭐ 23
This repository contains iCEBreaker examples for Amaranth HDL.
most recent commit 2 years ago
Awslabs ⭐ 23
most recent commit 5 years ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit a year ago
Accel Docker ⭐ 22
most recent commit 5 years ago
Microzed Axi Dma ⭐ 22
Demonstration of the AXI DMA engine on the MicroZed
most recent commit 3 years ago
Zipml Xeonfpga ⭐ 21
FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)
most recent commit 4 years ago
Cfm ⭐ 20
A 16-bit CPU and system, written in Haskell and running Forth on FPGA.
most recent commit 6 years ago
Limesdr Pcie ⭐ 20
most recent commit 7 years ago
Tart ⭐ 20
Transient Array Radio Telescope
dependent packages 3total releases 25most recent commit 2 years agopypi tart} Downloads
Fpu Sp ⭐ 19
IEEE 754 floating point library in system-verilog and vhdl
most recent commit 6 months ago
Hls Cnn ⭐ 19
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
most recent commit 5 months ago
Ovs Hw ⭐ 18
An open source hardware engine for Open vSwitch on FPGA
most recent commit 11 years ago
Chad ⭐ 18
A self-hosting Forth for J1-style CPUs
most recent commit 8 months ago
Fujprog ⭐ 18
FPGA ULX2/3 JTAG programmer
most recent commit 3 years ago
Handwritten Digit Recognition Painter ⭐ 18
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
most recent commit 6 months ago
Ovio_core ⭐ 18
most recent commit 3 years ago
Capi Textswap ⭐ 18
A "Hello World" for the Power8 CAPI Interface. Includes application C and RTL code.
most recent commit 9 years ago
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