Icecore
| Project Name | Stars | Downloads | Repos Using This | Packages Using This | Most Recent Commit | Total Releases | Latest Release | Open Issues | License | Language |
|---|---|---|---|---|---|---|---|---|---|---|
| Ice40_ultraplus_examples | 115 | 2 years ago | 3 | mpl-2.0 | Verilog | |||||
| Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation | ||||||||||
| Icecore | 18 | 5 years ago | 4 | C | ||||||
| IceCore Ice40 HX based modular core | ||||||||||
| Upduino | 11 | 5 years ago | 1 | Verilog | ||||||
| Up5k_riscv | 7 | 4 years ago | mit | AGS Script | ||||||
| There are many RISC V projects on iCE40. This one is mine. | ||||||||||
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