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An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores

A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores

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