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instruction-set-architecture x

16 search results found

Customasm ⭐ 643

💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/

Opcodes ⭐ 235

Database of CPU Opcodes

XCrypto: a cryptographic ISE for RISC-V

Rust Aluvm ⭐ 57

Rust implementation of AluVM (RISC functional machine)

UME::SIMD A library for explicit simd vectorization.

Riscv Assembler ⭐ 41

RISC-V Assembly code assembler package for Python.

Basic Simd Processor Verilog Tutorial ⭐ 41

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Mano Simulator ⭐ 31

🖥️ An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer.

Scarv Cpu ⭐ 18

SCARV: a side-channel hardened RISC-V platform

💾 The LC3 virtual machine

Katamaran ⭐ 16

Katamaran is a semi-automated separation logic verifier for the Sail specification language. It works on an embedded version of Sail called μSail and verifies separation logic-based contracts of functions by generating (succinct) first-order verification conditions.

Kite: Architecture Simulator for RISC-V Instruction Set

Risc Cpu ⭐ 10

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Stack Based Virtual Machine in Golang

Modular Graphical Simulator for Teaching Microprogramming

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