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Search results for cadence virtuoso
cadence-virtuoso
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15 search results found
Skillbridge
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140
A seamless python to Cadence Virtuoso Skill interface
Vlsi Fundamentals Education Kit
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122
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Basic Simd Processor Verilog Tutorial
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41
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
Analog Design Of 1.9 Ghz Pll System
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31
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
Cdsdm
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23
Cadence Virtuoso Design Management System
Rram_compiler
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20
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London
Ml2tikz
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16
maskLayout to tikzpicture converter for Cadence Virtuoso
Socad
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9
Connect Cadence Virtuoso to a Python client using sockets.
Veriloga Wave Generator
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9
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
Spam
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9
SKILL Package Manager
Analog Design Of Dynamic Comparator
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8
This project is about building a Clocked Comparator to be used in a 4-bit Flash ADC & minimize the ADC Figure of Merit given by FoM = Power / (fs*2ENOB).
Layout Design Of An 8x8 Sram Array
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8
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Sch2tikz
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8
schematic to tikzpicture converter for Cadence Virtuoso
Analog Design Of Asynchronous Sar Adc
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6
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
Smoc
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5
A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.
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1-15 of 15 search results
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