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The Top 23 Systemverilog Open Source Projects

Open source projects categorized as Systemverilog
Categories > Systemverilog
Zcash Fpga ⭐ 57
Zcash FPGA acceleration engine
most recent commit 4 years ago
Fpga Png Decoder ⭐ 57
An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图象解码器，可以从PNG文件中解码出原始像素。
most recent commit 8 months ago
Riscv Simple Sv ⭐ 56
A simple RISC V core for teaching
most recent commit 2 years ago
Nerv ⭐ 56
Naive Educational RISC V processor
most recent commit a year ago
Fpga Mpeg2 Encoder ⭐ 56
FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
most recent commit 8 months ago
Silver ⭐ 55
An attribute grammar-based programming language for composable language extensions
most recent commit 4 months ago
Ipxact2systemverilog ⭐ 55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
total releases 24most recent commit 5 months ago
Parallella Riscv ⭐ 55
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
most recent commit 5 years ago
Fpga Sata Hba ⭐ 54
A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
most recent commit 8 months ago
Floonoc ⭐ 53
A Fast, Low-Overhead On-chip Network
most recent commit 4 months ago
Vim Hdl ⭐ 53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
most recent commit 5 years ago
Fpga Sdcard Reader Spi ⭐ 52
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
most recent commit 8 months ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8most recent commit a year ago
Cheriot Ibex ⭐ 51
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
most recent commit 3 months ago
Enso ⭐ 50
Ensō is a high-performance streaming interface for NIC-application communication.
total releases 2most recent commit 4 months ago
Autosva ⭐ 50
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
most recent commit 5 months ago
Verilog Projects ⭐ 49
This repository contains source code for past labs and projects involving FPGA and Verilog based designs
most recent commit 5 years ago
Zerosoc ⭐ 48
Demo SoC for SiliconCompiler.
most recent commit 4 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11most recent commit 6 months agopypi peakrdl} Downloads
Design Pattern In Sv ⭐ 48
This repo is created to include illustrative examples on object oriented design pattern in SV
most recent commit a year ago
Bigpulp ⭐ 48
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
most recent commit 2 years ago
Sv Tutorial ⭐ 47
SystemVerilog Tutorial
most recent commit 5 months ago
S32x_mister ⭐ 47
Sega 32X implementation for MiSTer
most recent commit 5 months ago
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