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The Top 12 Verilog Systemverilog Verilator Open Source Projects

Open source projects categorized as Verilog Systemverilog Verilator
Categories > Systemverilog
Categories > Verilator
Categories > Hardware > Verilog
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8most recent commit 3 months ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Vscode Verilog Hdl Support ⭐ 266
HDL support for VS Code
most recent commit 3 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Svut ⭐ 59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
total releases 2most recent commit a year ago
Virtio ⭐ 18
Virtio implementation in SystemVerilog
most recent commit 6 years ago
Svreal ⭐ 11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
total releases 26most recent commit 3 years ago
Nirah ⭐ 11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
most recent commit 5 years ago
Croyde Riscv ⭐ 10
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
most recent commit 2 years ago
Linter Veriloghdl ⭐ 6
Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
most recent commit 9 months ago
Pci Edu ⭐ 6
SystemVerilog implemention of QEMU PCI edu device
most recent commit a year ago
Go.debug ⭐ 5
Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster
total releases 3most recent commit 3 years ago
The 2 Most Depended On Verilog Systemverilog Verilator Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8latest release October 04, 2022most recent commit 3 months ago
The 5 Latest Releases In Verilog Systemverilog Verilator Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Svut ⭐ 59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
total releases 2latest release October 27, 2022most recent commit a year ago
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8latest release October 04, 2022most recent commit 3 months ago
Svreal ⭐ 11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
total releases 26latest release November 13, 2020most recent commit 3 years ago
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