Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About

The Top 23 Verilog Risc V Open Source Projects

Open source projects categorized as Verilog Risc V
Categories > Hardware > Risc V
Categories > Hardware > Verilog
Vexriscv ⭐ 2,135
A FPGA friendly 32 bit RISC-V CPU implementation
most recent commit 4 months ago
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
E200_opensource ⭐ 1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
most recent commit 3 years ago
Neorv32 ⭐ 1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
most recent commit 3 months ago
Serv ⭐ 1,158
SERV - The SErial RISC-V CPU
most recent commit 4 months ago
Vortex ⭐ 939
most recent commit 3 months ago
E203_hbirdv2 ⭐ 741
The Ultra-Low Power RISC-V Core
most recent commit a year ago
Scr1 ⭐ 688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
most recent commit 7 months ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Kianriscv ⭐ 396
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
most recent commit 4 months ago
Risc V Single Cycle Cpu ⭐ 380
A RISC-V 32bit single-cycle CPU written in Logisim
most recent commit a year ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Verigpu ⭐ 323
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
most recent commit a year ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 8 months ago
Ridecore ⭐ 185
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
most recent commit 7 years ago
Riscv Bitmanip ⭐ 174
Working draft of the proposed RISC-V Bitmanipulation extension
most recent commit a year ago
Fomu Workshop ⭐ 148
Support files for participating in a Fomu workshop
most recent commit a year ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Ice40_ultraplus_examples ⭐ 115
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
most recent commit 2 years ago
Srv32 ⭐ 109
Simple 3-stage pipeline RISC-V processor
most recent commit 5 months ago
Icestation 32 ⭐ 107
Compact FPGA game console
most recent commit 3 years ago
Tang_e203_mini ⭐ 103
LicheeTang 蜂鸟E203 Core
most recent commit 5 years ago
Popular Hardware Categories
Arduino
Raspberry Pi
Camera
Sensor
Gpu
Firmware
Usb
Keyboard
Cpu
Arm
Categories
Privacy | About | Terms | Follow Us On Twitter

Downloads, Dependent Repos, Dependent Packages, Total Releases, Latest Releases data powered by Libraries.io.

Copyright 2018-2024 Awesome Open Source.  All rights reserved.