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The Top 20 Pipeline Verilog Open Source Projects

Open source projects categorized as Pipeline Verilog
Categories > Data Processing > Pipeline
Categories > Hardware > Verilog
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
Xls ⭐ 1,087
XLS: Accelerated HW Synthesis
most recent commit 3 months ago
Verilog Fixedpoint ⭐ 75
A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
most recent commit 8 months ago
Bch_verilog ⭐ 57
Verilog based BCH encoder/decoder
most recent commit 2 years ago
Mips Pipeline Processor ⭐ 52
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
most recent commit 5 years ago
Autopiper ⭐ 40
most recent commit 9 years ago
Risc V Cpu ⭐ 34
RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
most recent commit 6 years ago
Computer Architecture Task 2 ⭐ 25
Riscv32 CPU Project
most recent commit 6 years ago
Fast ⭐ 22
FAST
most recent commit 7 years ago
Tinycpu ⭐ 21
Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
most recent commit 12 years ago
Mips Cpu ⭐ 11
The Verilog implementation of five-stage-pipelined MIPS CPU (Classic RISC pipeline)
most recent commit 3 years ago
Bextdep ⭐ 10
Reference Hardware Implementations of Bit Extract/Deposit Instructions
most recent commit 7 years ago
Riscv Core ⭐ 9
5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
most recent commit 5 months ago
Mips Architecture Cpu Design ⭐ 9
BUAA SCSE - Computer Organization - Pipeline CPU design
most recent commit 5 years ago
Mips Simulator ⭐ 9
💻 A 5-stage pipeline MIPS CPU design in Haskell.
most recent commit 4 years ago
Arm Architecture ⭐ 7
A pipelined ARM architecture implementation using Verilog and evaluation by the Bubble sorting algorithm on FPGA
most recent commit a year ago
Tomasulo ⭐ 6
An out-of-order execution algorithm for pipeline CPU, implemented by verilog
most recent commit 6 years ago
Superscalar_pipeline_processor ⭐ 5
Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.
most recent commit 7 years ago
Anppv_risc_pipelinedprocessor ⭐ 5
most recent commit 7 years ago
Mips Cpu ⭐ 5
Xilinx Project for MIPS CPU
most recent commit 6 years ago
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