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The Top 17 Open Source Verilog Open Source Projects

Open source projects categorized as Open Source Verilog
Categories > Legal > Open Source
Categories > Hardware > Verilog
Xls ⭐ 1,087
XLS: Accelerated HW Synthesis
most recent commit 3 months ago
Beagle_sdr_gps ⭐ 446
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
most recent commit 3 months ago
Openfpgaduino ⭐ 135
All open source file and project for OpenFPGAduino project
most recent commit 5 years ago
Sofa ⭐ 111
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
most recent commit a year ago
Haasoscope ⭐ 107
Docs, design, firmware, and software for the Haasoscope
most recent commit 3 months ago
Xcrypto ⭐ 80
XCrypto: a cryptographic ISE for RISC-V
most recent commit a year ago
Aib Phy Hardware ⭐ 57
most recent commit a year ago
Open Src Cvc ⭐ 32
Mirror of tachyon-da cvc Verilog simulator
most recent commit 9 months ago
Ophidian ⭐ 29
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
most recent commit 4 years ago
Shunt ⭐ 29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
most recent commit 4 months ago
E Verest ⭐ 29
EVEREST: e-Versatile Research Stick for peoples
most recent commit a year ago
Scarv Cpu ⭐ 18
SCARV: a side-channel hardened RISC-V platform
most recent commit a year ago
Getting Started With Verilog ⭐ 12
Verilog modules for beginners
most recent commit 2 years ago
Yosys Tcl Ui Report ⭐ 12
5 Day TCL begginer to advanced training workshop by VSD
most recent commit 6 months ago
Awesome Eda ⭐ 9
most recent commit 5 years ago
Openxc7 Tetrisaraj ⭐ 7
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
most recent commit 4 months ago
Gvi ⭐ 5
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
most recent commit 5 months ago
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