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The Top 23 C Verilog Fpga Open Source Projects

Open source projects categorized as C Verilog Fpga
Openwifi ⭐ 3,363
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
most recent commit 5 months ago
Nyuziprocessor ⭐ 1,863
GPGPU microprocessor architecture
most recent commit 3 months ago
Metron ⭐ 143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
most recent commit 4 months ago
Openfpgaduino ⭐ 135
All open source file and project for OpenFPGAduino project
most recent commit 5 years ago
Zynq7010_eink_controller ⭐ 133
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
most recent commit 8 months ago
Icestation 32 ⭐ 107
Compact FPGA game console
most recent commit 3 years ago
Fpga Rocket Chip ⭐ 79
Wrapper for Rocket-Chip on FPGAs
most recent commit 2 years ago
Keyboard ⭐ 72
客制化机械键盘——从0开始全套资料
most recent commit 9 months ago
Cep ⭐ 53
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
most recent commit a year ago
Spu32 ⭐ 48
Small Processing Unit 32: A compact RV32I CPU written in Verilog
most recent commit 2 years ago
Pdp6 ⭐ 45
PDP-6 Emulator
most recent commit 2 years ago
Super Miyamoto Sprint ⭐ 41
Homebrew game for homebrew FPGA game console
most recent commit 3 years ago
Usb_sniffer ⭐ 40
High Speed USB 2.0 capture device based on miniSpartan6+
most recent commit 4 years ago
Fpga101 Workshop ⭐ 38
FPGA 101 - Workshop materials
most recent commit 5 years ago
Grassrootsstartup Computervsion Zynq ⭐ 35
most recent commit a year ago
Riscv_cpu ⭐ 30
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
most recent commit 4 years ago
Yari ⭐ 24
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
most recent commit 5 years ago
Bgbtech_btsr1arch ⭐ 17
BtSR1 and BJX2 ISA / CPU Architecture
most recent commit 3 months ago
Sea ⭐ 15
most recent commit 4 years ago
Jtag_interface ⭐ 14
A template for establishing a JTAG connection between the MCU and FPGA chip on the Arduino MKR Vidor 4000
most recent commit 4 months ago
Zynq Aes ⭐ 11
AES hardware engine for Xilinx Zynq platform
most recent commit 3 years ago
Toast Rv32i ⭐ 11
A Pipelined RISC-V RV32I Core in Verilog
most recent commit 3 years ago
Icore ⭐ 10
in-line FPGA-CPU协同分组处理
most recent commit 2 years ago
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