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The Top 19 Hardware Asic Open Source Projects

Open source projects categorized as Hardware Asic
Categories > Hardware > Asic
Categories > Hardware > Hardware
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Progpow ⭐ 243
A Programmatic Proof-of-Work for Ethash. Forked from https://github.com/ethereum-mining/ethminer
most recent commit 3 years ago
Ztachip ⭐ 172
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
most recent commit 3 months ago
Skillbridge ⭐ 140
A seamless python to Cadence Virtuoso Skill interface
dependent packages 3total releases 44most recent commit 5 months agopypi skillbridge} Downloads
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21most recent commit 2 years agopypi pygears} Downloads
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3most recent commit 7 months ago
Awesome Hwd Tools ⭐ 41
A curated list of awesome open source hardware design tools
most recent commit a year ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit a year ago
Chad ⭐ 18
A self-hosting Forth for J1-style CPUs
most recent commit 8 months ago
Open Cryptonight Asic ⭐ 16
Open source hardware implementation of classic CryptoNight
most recent commit 6 years ago
Hdl Modules ⭐ 10
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
most recent commit 3 months ago
P4 Info ⭐ 10
most recent commit 3 years ago
Cpu7 ⭐ 9
most recent commit a year ago
Mastering Fpgasic Book ⭐ 8
📖 Mastering FPGASIC Book
most recent commit 2 years ago
Spinalhdl Template ⭐ 8
Mill template for beginning your SpinalHDL project
most recent commit a year ago
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3most recent commit 2 years ago
Instrumented_adder ⭐ 6
Instrumenting adders to measure speed
most recent commit 2 years ago
Tinyuart ⭐ 5
Lightweight UART core in VHDL
most recent commit 2 years ago
Hashpool ⭐ 5
Efficient Library software for Miners and Pools
most recent commit 3 months ago
The 3 Most Depended On Hardware Asic Open Source Projects
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Skillbridge ⭐ 140
A seamless python to Cadence Virtuoso Skill interface
dependent packages 3total releases 44latest release August 18, 2023most recent commit 5 months agopypi skillbridge} Downloads
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
The 4 Latest Releases In Hardware Asic Open Source Projects
Dfiant ⭐ 56
DFiant: A Dataflow Hardware Descripition Language
dependent packages 4total releases 3latest release September 05, 2023most recent commit 7 months ago
Skillbridge ⭐ 140
A seamless python to Cadence Virtuoso Skill interface
dependent packages 3total releases 44latest release August 18, 2023most recent commit 5 months agopypi skillbridge} Downloads
Libsv ⭐ 6
An open source, parameterized SystemVerilog digital hardware IP library
total releases 3latest release January 31, 2022most recent commit 2 years ago
Pygears ⭐ 93
HW Design: A Functional Approach
dependent packages 1total releases 21latest release October 28, 2018most recent commit 2 years agopypi pygears} Downloads
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