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Riscvspecformal
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58
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Smachine
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32
Simple Machine, include simulator、ccompiler、assembler
Futile
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8
lightweight functional/blackbox/acceptance testing package for web pages
Gcc 4.6.4
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5
Patch to gcc for supporting "fastcall" and "regparm" on m68k target.
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