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Haskell library for hardware description

Riscvspecformal ⭐ 58

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Transactional cache with configurable persistence

high-resolution performance benchmarking

Register Machine Type ⭐ 19

Universal Register Machine implemented at the type-level of Haskell

run and encode simple register machine programs

Portable high-level assembler with authentic C syntax

Ghc Simd Tests ⭐ 9

Compiles a subset of Java to MIPS assembly

Haskell Demolicious compiler

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