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17 search results found

Opentimer ⭐ 368

A High-performance Timing Analysis Tool for VLSI Systems

A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

Gds2para ⭐ 76

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

Spydrnet ⭐ 66

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Fan_atpg ⭐ 51

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

Parser Spef ⭐ 29

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

Parser Verilog ⭐ 24

A Standalone Structural Verilog Parser

Nthu Route ⭐ 21

VLSI EDA Global Router

AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!

Naja Verilog ⭐ 18

A standalone structural (gate-level) verilog parser

Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

Partlocater ⭐ 9

Find a part on Digi-Key and import parameters into local database

EDA Analytics Central

Edaoncloud ⭐ 7

Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)

Provides a packaged collection of open source EDA tools

Tf Parser ⭐ 6

Technology file parser in Rust

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1-17 of 17 search results

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