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Zynqnet ⭐ 510

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"

Lenet5_hls ⭐ 188

FPGA Accelerator for CNN using Vivado HLS

Fpga Zynqnet ⭐ 56

FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS

Cnn_fpga_zynq_pynq ⭐ 20

hls code zynq 7020 pynq z2 CNN

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

Cnn Using Hls ⭐ 15

Convolutional Neural Network Using High Level Synthesis

Hls Lenet ⭐ 13

The CNN based on the Xilinx Vivado HLS

Simpletpu ⭐ 9

A CNN accelerator, following Google's TPU V1.

Handwritten_mathematical_calculator_on_fpga ⭐ 8

A simple demo to implement the Handwritten Mathematical Calculator on PYNQ-Z2 FPGA platform by using HLS.

Pynq Cnn Attempt ⭐ 7

Some attempts to build CNN on PYNQ.

Lenet5 Accelerator ⭐ 5

FPGA and GPU acceleration of LeNet5

Visual System Integrator ⭐ 5

Visual System Integrator - Accelerate your embedded development

Landmark Detection with CNN on FPGA including DPR

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