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42 search results found

Tengine ⭐ 4,452

Tengine is a lite, high performance, modular inference engine for embedded device

Ripes ⭐ 2,266

A graphical processor simulator and assembly editor for the RISC-V ISA

The official repository for the gem5 computer-system architecture simulator.

Risc0 ⭐ 1,231

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

Libriscv ⭐ 371

C++20 RISC-V RV32/64/128 userspace emulator library

World Of Warcraft 3.3.5a server

Projects ⭐ 307

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8

Mipt Mips ⭐ 291

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

Cpp Stub ⭐ 235

C++ unit test stub(not mock) and awesome.Surpported ISA x86,x86-64,arm64,arm32,arm thumb,mips64,riscv,loongarch64.

Rvscript ⭐ 203

Fast RISC-V-based scripting backend for game engines

Force Riscv ⭐ 183

Instruction Set Generator initially contributed by Futurewei

Qtrvsim ⭐ 179

RISC-V CPU simulator for education purposes

Emoji Shellcoding ⭐ 124

🤩 Emoji shellcoding tools for RISC-V (32-bit and 64-bit)

fdtd3d is an open source 1D, 2D, 3D FDTD electromagnetics solver with MPI, OpenMP and CUDA support for x64, ARM, ARM64, RISC-V, PowerPC architectures

Objex_link ⭐ 95

OBJEX Link is a modular IoT board. It is designed to develop IoT devices that are easy to repair and recycle. It is also perfect for rapid prototyping and developing research and robotics projects.

Riscv Perf Model ⭐ 80

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.

Marss Riscv ⭐ 60

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

Kobayashi Compiler ⭐ 55

An optimizing compiler of SysY (a subset of C)

Riscv Vectorized Benchmark Suite ⭐ 48

RiVEC Bencmark Suite

Riscv Simulator ⭐ 41

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

Lndso150 ⭐ 40

Newer alternative firmware for the DSO150/DSO shell small oscilloscope

Swimmer_riscv ⭐ 34

Instruction set simulator for RISC-V

Gd32vf103inator ⭐ 33

Program the GD32VF103 using C, your favourite editor and make

Percival ⭐ 32

Open-Source Posit RISC-V Core with Quire Capability

A RISC-V simulator

Dbt Rise Riscv ⭐ 30

An instruction set simulator based on DBT-RISE implementing the RISC-V ISA

Exactstep ⭐ 29

Instruction set simulator for RISC-V, MIPS and ARM-v6m

Riscv Alphanumeric Shellcoding ⭐ 28

Alphanumeric+1 shellcoding tools for RISC-V

A runtime code generator for RISC-V

Lightweight and performant dynamic binary translation for RISC–V code on x86–64

Riscv Parser ⭐ 26

Basis of a RISC-V parser to be used for linters or assemblers.

Extendable Translating Instruction Set Simulator

RISC-V Dynamic Debugging Tool

Iar Risc V Gd32v Eval ⭐ 24

Example projects for the IAR RISC-V GD32V Evaluation board in IAR Embedded Workbench for RISC-V

JIT-accelerated RISC-V instruction set simulator

An unofficial reference implementation of the C Minus Minus Compiler

Open source ISS and logic RISC-V 32 bit project

Risc 666 ⭐ 20

RISC-V user-mode emulator that runs DooM

Riscv Simulator ⭐ 19

PKU computer organization and architecture RISC-V Simulator LAB

The Gee (寂) Operating System, written in YuLang.

M5stamp C3dev ⭐ 17

This is a development board for the M5Stamp C3 (RISC-V/FreeRTOS).

Corepartition ⭐ 16

Universal Cooperative Multithread Lib with real time Scheduler that was designed to work, virtually, into any modern micro controller or Microchip and, also, for user space applications for modern OS (Mac, Linux, Windows) or on FreeRTOS as well. Supports C and C++

The ParaNut Processor - Highly Parallel and More Than Just a CPU Core

Symex Vp ⭐ 14

A concolic testing engine for RISC-V embedded software with support for SystemC peripherals

Riscv Atom ⭐ 14

An open-source 32-bit RISC-V soft-core processor for FPGAs.

Rv32i Sim ⭐ 14

RISC-V Software Simulation

M99_riscv_emulator ⭐ 11

Simple RISC-V emulator

Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension

Pure C++ non stack displacement that implements cooperative multitask library for SINGLE CORE embedded development on DSPs, Microcontrollers and Processor (ARV, RISCV, ARM(all), TENSY, ESP), while also suitable for applications on Windows, Linux and MacOs and compatible with some RTOSs as well. This library allows full event driven applications while uses SMARTs LOCKS and WAIT/NOTIFY locks to also transport messages, MESSAGE BROKER is also provided (Those uses Message type size_t message and si

Machine Tests ⭐ 10

Cartesi machine tests

Machine Emulator Rom ⭐ 9

Cartesi Machine Emulator ROM

Toy RISC-V emulator

A compiler for a subset of C11 language. Under development...

Riscv Hpmcounters ⭐ 8

A simple utility for doing RISC-V HPM perf monitoring.

32-bit soft RISCV processor for FPGA applications

Vcb Riscv ⭐ 7

Virtual Circuit Board RISC-V

RISC-V Virtual Prototype

Cpu Judge ⭐ 7

Hifive1 Vp ⭐ 7

A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS

Modern Cxx Riscv ⭐ 7

Baremetal RISC-V examples with modern C++

A Small RISC-V Virtual Machine

A RISCV processor in system verilog

Cade Andgreg's Risc-V Emulator

Pint_iverilog ⭐ 5

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

The Scale4Edge ecosystem VP

DUTH RISC V Microprocessor for High Level Synthesis

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1-42 of 42 search results

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