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The Top 8 Parser Systemverilog Verilog Open Source Projects
Open source projects categorized as Parser Systemverilog Verilog
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dalance/sv-parser
⭐
348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages
0
total releases
0
most recent commit
over 2 years ago
chipsalliance/Surelog
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312
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
dependent packages
0
total releases
0
most recent commit
over 2 years ago
Nic30/hdlConvertor
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258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages
0
total releases
0
most recent commit
over 2 years ago
ben-marshall/verilog-vcd-parser
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28
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
dependent packages
0
total releases
0
most recent commit
over 4 years ago
sgherbst/svinst
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18
Determines the modules declared and instantiated in a SystemVerilog file
dependent packages
0
total releases
0
most recent commit
almost 4 years ago
clin99/awesome-eda
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9
dependent packages
0
total releases
0
most recent commit
almost 7 years ago
sgherbst/pysvinst
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8
Python library for parsing module definitions and instantiations from SystemVerilog files
dependent packages
0
total releases
0
most recent commit
about 5 years ago
cclienti/svmodule
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6
SystemVerilog & Verilog Module I/O parser and printer
dependent packages
0
total releases
0
most recent commit
almost 5 years ago
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