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The Top 23 Xilinx Vivado Open Source Projects

Open source projects categorized as Xilinx Vivado
Categories > Vivado
Categories > Xilinx
Fpga ⭐ 1,103
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
most recent commit 2 years ago
Hdmi ⭐ 892
Send video/audio over HDMI on an FPGA
most recent commit 8 months ago
Prjxray ⭐ 731
Documenting the Xilinx 7-series bit-stream format.
most recent commit 24 days ago
Vivado Risc V ⭐ 682
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
most recent commit 3 months ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Rapidwright ⭐ 262
Build Customized FPGA Implementations for Vivado
dependent packages 1total releases 69most recent commit 3 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Tinytpu ⭐ 111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
most recent commit 5 years ago
Intfftk ⭐ 56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
most recent commit a year ago
Hyperram ⭐ 33
Portable HyperRAM controller
most recent commit 5 months ago
Prjuray ⭐ 33
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
most recent commit 2 years ago
Pyfpga ⭐ 31
A Python package to use FPGA development tools programmatically.
most recent commit 2 years ago
Arm Legv8 ⭐ 29
Verilog Implementation of an ARM LEGv8 CPU
most recent commit 6 years ago
Custom_part_data_files ⭐ 28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
most recent commit 4 months ago
Hwac_object_tracker ⭐ 24
FPGA accelerated TinyYOLO v2 object detection neural network
most recent commit 6 years ago
Scoreboard Wtimer ⭐ 23
Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
most recent commit 3 months ago
Ebaz4205 ⭐ 22
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
most recent commit 2 years ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit a year ago
Openhbmc ⭐ 21
Open-source high performance AXI4-based HyperRAM memory controller
most recent commit 2 years ago
Eda Scripts ⭐ 20
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
most recent commit 6 months ago
Virtio ⭐ 18
Virtio implementation in SystemVerilog
most recent commit 6 years ago
Vivado Docker ⭐ 16
Dockerfile with Vivado for CI
most recent commit 4 years ago
Vdt Plugin ⭐ 15
mirror of https://git.elphel.com/Elphel/vdt-plugin
most recent commit 6 years ago
The 2 Most Depended On Xilinx Vivado Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Rapidwright ⭐ 262
Build Customized FPGA Implementations for Vivado
dependent packages 1total releases 69latest release November 20, 2023most recent commit 3 months ago
The 2 Latest Releases In Xilinx Vivado Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Rapidwright ⭐ 262
Build Customized FPGA Implementations for Vivado
dependent packages 1total releases 69latest release November 20, 2023most recent commit 3 months ago
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