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The Top 23 Verilog Vivado Open Source Projects

Open source projects categorized as Verilog Vivado
Categories > Hardware > Verilog
Categories > Vivado
Fpga ⭐ 1,103
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
most recent commit 2 years ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Vscode Verilog Hdl Support ⭐ 266
HDL support for VS Code
most recent commit 3 months ago
Image Processing ⭐ 123
Image Processing Toolbox in Verilog using Basys3 FPGA
most recent commit 7 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Tinytpu ⭐ 111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
most recent commit 5 years ago
Cnn_for_slr ⭐ 79
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
most recent commit 4 months ago
Intfftk ⭐ 56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
most recent commit a year ago
Fixed Floating Point Adder Multiplier ⭐ 42
16-bit Adder Multiplier hardware on Digilent Basys 3
most recent commit 9 months ago
Arm Legv8 ⭐ 29
Verilog Implementation of an ARM LEGv8 CPU
most recent commit 6 years ago
Custom_part_data_files ⭐ 28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
most recent commit 4 months ago
Fpga_qpsk Modem ⭐ 26
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
most recent commit 5 months ago
Hwac_object_tracker ⭐ 24
FPGA accelerated TinyYOLO v2 object detection neural network
most recent commit 6 years ago
Scoreboard Wtimer ⭐ 23
Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
most recent commit 3 months ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit 10 months ago
Openhbmc ⭐ 21
Open-source high performance AXI4-based HyperRAM memory controller
most recent commit 2 years ago
Virtio ⭐ 18
Virtio implementation in SystemVerilog
most recent commit 6 years ago
Deep Darkfantasy ⭐ 15
Global Dark Mode for ALL apps on ANY platforms.
most recent commit 3 years ago
Sha256hasher ⭐ 15
SHA-256 IP core for ZedBoard (Zynq SoC)
most recent commit 6 years ago
Vdt Plugin ⭐ 15
mirror of https://git.elphel.com/Elphel/vdt-plugin
most recent commit 6 years ago
F4pga Xc7 Bram Patch ⭐ 12
Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
most recent commit 2 years ago
Rules_vivado ⭐ 11
Bazel rules for Xilinx Vivado
most recent commit 2 years ago
Svreal ⭐ 11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
total releases 26most recent commit 3 years ago
The 2 Latest Releases In Verilog Vivado Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Svreal ⭐ 11
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
total releases 26latest release November 13, 2020most recent commit 3 years ago
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