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The Top 23 Verilog Tcl Open Source Projects

Open source projects categorized as Verilog Tcl
Basic_verilog ⭐ 1,333
Must-have verilog systemverilog modules
most recent commit 4 months ago
Openroad ⭐ 1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
most recent commit 3 months ago
Openroad Flow Scripts ⭐ 233
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/la
most recent commit 3 months ago
Vsdflow ⭐ 121
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Ope
most recent commit a year ago
Fpgamake ⭐ 78
Generates Makefiles to synthesize, place, and route verilog using Vivado
most recent commit 2 years ago
Skrskr ⭐ 76
The second place winner for DAC-SDC 2020
most recent commit 2 years ago
Openphysyn ⭐ 46
EDA physical synthesis optimization kit
most recent commit 5 months ago
Ddlm ⭐ 42
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
most recent commit 7 months ago
Custom_part_data_files ⭐ 28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
most recent commit 4 months ago
Cis501 ⭐ 18
CIS 501: Computer Architecture Fall 2019
most recent commit 4 years ago
Ece1373_2016_hft_on_fpga ⭐ 16
High Frequency Trading using Vivado HLS
most recent commit 7 years ago
Asynchronous Verilog Synthesiser ⭐ 14
Synthesiser for Asynchronous Verilog Language
most recent commit 9 years ago
Study Materials ⭐ 12
most recent commit a year ago
Yosys Tcl Ui Report ⭐ 12
5 Day TCL begginer to advanced training workshop by VSD
most recent commit 6 months ago
Nldb ⭐ 10
Verilog netlist parser/database (derived from http://nldb.sourceforge.net)
most recent commit 9 years ago
32 Point Fft Verilog Design Based Dit Butterfly Algorithm ⭐ 10
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
most recent commit 9 months ago
Icglue ⭐ 9
A Tcl-Library for scripted HDL generation
most recent commit a year ago
Source_to_inst ⭐ 9
This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in their design.
most recent commit 11 years ago
Pymtl Tut Hls ⭐ 8
Tutorial for integrating PyMTL and Vivado HLS
most recent commit 8 years ago
Sky130rhbdlib ⭐ 7
Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
most recent commit a year ago
Verilog Spi ⭐ 7
This is a SPI Master Module Written in Verilog
most recent commit 6 years ago
Hdu_co_guide ⭐ 6
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
most recent commit 5 years ago
F4pga Xc Fasm2bels ⭐ 6
Library to convert a FASM file into BELs importable into Vivado.
most recent commit a year ago
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