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The Top 23 Verilog Systemverilog Open Source Projects

Open source projects categorized as Verilog Systemverilog
Categories > Systemverilog
Categories > Hardware > Verilog
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8most recent commit 3 months ago
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Scr1 ⭐ 688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
most recent commit 7 months ago
Minecrafthdl ⭐ 595
A Verilog synthesis flow for Minecraft redstone circuits
most recent commit 3 years ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Slang ⭐ 505
SystemVerilog compiler and language services
most recent commit 3 months ago
Projf Explore ⭐ 478
Project F brings FPGAs to life with exciting open-source designs you can build on.
most recent commit 3 months ago
Vscode Teroshdl ⭐ 457
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
most recent commit 3 months ago
Sv2v ⭐ 429
SystemVerilog to Verilog conversion
total releases 4most recent commit 3 months ago
Svls ⭐ 376
SystemVerilog language server
total releases 40most recent commit 3 months ago
Sv Parser ⭐ 348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 5total releases 58most recent commit 5 months agocargo sv-parser} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30most recent commit 19 days agopypi pymtl3} Downloads
Surelog ⭐ 325
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
total releases 1most recent commit 2 months ago
Verigpu ⭐ 323
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
most recent commit a year ago
Fpga Foc ⭐ 319
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
most recent commit 7 months ago
Vscode Verilog Hdl Support ⭐ 266
HDL support for VS Code
most recent commit 3 months ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19most recent commit 3 months agopypi hdlConvertor} Downloads
Sv Tests ⭐ 257
Test suite designed to check compliance with the SystemVerilog standard.
most recent commit a month ago
Svlint ⭐ 254
SystemVerilog linter
dependent packages 1total releases 61most recent commit 4 months agocargo svlint} Downloads
Verilog Mode ⭐ 231
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
most recent commit 3 months ago
Veryl ⭐ 225
Veryl: A Modern Hardware Description Language
dependent packages 7total releases 31most recent commit 3 months agocargo veryl-parser} Downloads
The 10 Most Depended On Verilog Systemverilog Open Source Projects
Veryl ⭐ 225
Veryl: A Modern Hardware Description Language
dependent packages 7total releases 31latest release October 19, 2023most recent commit 3 months agocargo veryl-parser} Downloads
Sv Parser ⭐ 348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 5total releases 58latest release November 29, 2023most recent commit 5 months agocargo sv-parser} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Svlint ⭐ 254
SystemVerilog linter
dependent packages 1total releases 61latest release November 20, 2023most recent commit 4 months agocargo svlint} Downloads
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19latest release July 02, 2021most recent commit 3 months agopypi hdlConvertor} Downloads
Cosa ⭐ 35
CoreIR Symbolic Analyzer
dependent packages 1total releases 16latest release June 03, 2019most recent commit 3 years agopypi CoSA} Downloads
The 10 Latest Releases In Verilog Systemverilog Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Sv Parser ⭐ 348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 5total releases 58latest release November 29, 2023most recent commit 5 months agocargo sv-parser} Downloads
Ipxact2systemverilog ⭐ 55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
total releases 24latest release November 26, 2023most recent commit 5 months ago
Svls ⭐ 376
SystemVerilog language server
total releases 40latest release November 20, 2023most recent commit 3 months ago
Svlint ⭐ 254
SystemVerilog linter
dependent packages 1total releases 61latest release November 20, 2023most recent commit 4 months agocargo svlint} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Veryl ⭐ 225
Veryl: A Modern Hardware Description Language
dependent packages 7total releases 31latest release October 19, 2023most recent commit 3 months agocargo veryl-parser} Downloads
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