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The Top 23 Systemverilog Open Source Projects

Open source projects categorized as Systemverilog
Categories > Systemverilog
Opentitan ⭐ 2,108
OpenTitan: Open source silicon root of trust
most recent commit 3 months ago
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8most recent commit 3 months ago
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87most recent commit 3 months ago
Verible ⭐ 1,179
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
most recent commit 20 days ago
Ibex ⭐ 1,169
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
most recent commit 3 months ago
Hdmi ⭐ 892
Send video/audio over HDMI on an FPGA
most recent commit 8 months ago
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Rsd ⭐ 824
RSD: RISC-V Out-of-Order Superscalar Processor
most recent commit 5 months ago
Swerv_eh1 ⭐ 746
A directory of Western Digital’s RISC-V SweRV Cores
most recent commit 4 years ago
Scr1 ⭐ 688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
most recent commit 7 months ago
Lets Prove Leftpad ⭐ 598
Proving leftpad correct in a dozen different ways
most recent commit 4 months ago
Minecrafthdl ⭐ 595
A Verilog synthesis flow for Minecraft redstone circuits
most recent commit 3 years ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Pcileech Fpga ⭐ 525
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
most recent commit 3 months ago
Slang ⭐ 505
SystemVerilog compiler and language services
most recent commit 3 months ago
Black Parrot ⭐ 494
A Linux-capable RISC-V multicore for and by the world
most recent commit 3 months ago
Projf Explore ⭐ 478
Project F brings FPGAs to life with exciting open-source designs you can build on.
most recent commit 3 months ago
Vscode Teroshdl ⭐ 457
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
most recent commit 3 months ago
Sv2v ⭐ 429
SystemVerilog to Verilog conversion
total releases 4most recent commit 3 months ago
Basejump_stl ⭐ 421
BaseJump STL: A Standard Template Library for SystemVerilog
most recent commit 3 months ago
Common_cells ⭐ 384
Common SystemVerilog components
most recent commit 4 months ago
Svls ⭐ 376
SystemVerilog language server
total releases 40most recent commit 3 months ago
Pulp ⭐ 364
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
most recent commit 7 months ago
The 10 Most Depended On Systemverilog Open Source Projects
Veryl ⭐ 225
Veryl: A Modern Hardware Description Language
dependent packages 7total releases 31latest release October 19, 2023most recent commit 3 months agocargo veryl-parser} Downloads
Sv Parser ⭐ 348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 5total releases 58latest release November 29, 2023most recent commit 5 months agocargo sv-parser} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Rggen Systemverilog ⭐ 9
SystemVerilog RTL and UVM RAL model generators for RgGen
dependent packages 3total releases 30latest release September 12, 2023most recent commit 3 months agorubygems rggen-systemverilog} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Svlint ⭐ 254
SystemVerilog linter
dependent packages 1total releases 61latest release November 20, 2023most recent commit 4 months agocargo svlint} Downloads
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19latest release July 02, 2021most recent commit 3 months agopypi hdlConvertor} Downloads
The 10 Latest Releases In Systemverilog Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Sv Parser ⭐ 348
SystemVerilog parser library fully compliant with IEEE 1800-2017
dependent packages 5total releases 58latest release November 29, 2023most recent commit 5 months agocargo sv-parser} Downloads
Ipxact2systemverilog ⭐ 55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
total releases 24latest release November 26, 2023most recent commit 5 months ago
Svls ⭐ 376
SystemVerilog language server
total releases 40latest release November 20, 2023most recent commit 3 months ago
Svlint ⭐ 254
SystemVerilog linter
dependent packages 1total releases 61latest release November 20, 2023most recent commit 4 months agocargo svlint} Downloads
Clash Compiler ⭐ 1,336
Haskell to VHDL/Verilog/SystemVerilog compiler
total releases 87latest release November 11, 2023most recent commit 3 months ago
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 6 months agopypi peakrdl} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Veryl ⭐ 225
Veryl: A Modern Hardware Description Language
dependent packages 7total releases 31latest release October 19, 2023most recent commit 3 months agocargo veryl-parser} Downloads
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