Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About

The Top 23 Risc V Soc Open Source Projects

Open source projects categorized as Risc V Soc
Categories > Hardware > Risc V
Categories > Soc
Vexriscv ⭐ 2,135
A FPGA friendly 32 bit RISC-V CPU implementation
most recent commit 3 months ago
Chipyard ⭐ 1,393
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
most recent commit 19 days ago
Neorv32 ⭐ 1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
most recent commit 3 months ago
Riscv Cores List ⭐ 778
RISC-V Cores, SoC platforms and SoCs
most recent commit 3 years ago
E203_hbirdv2 ⭐ 741
The Ultra-Low Power RISC-V Core
most recent commit a year ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Pulp Dronet ⭐ 428
A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
most recent commit 2 years ago
F32c ⭐ 390
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
most recent commit 3 months ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Saxonsoc ⭐ 133
SoC based on VexRiscv and ICE40 UP5K
most recent commit 3 months ago
Tang_e203_mini ⭐ 103
LicheeTang 蜂鸟E203 Core
most recent commit 5 years ago
Nuclei Sdk ⭐ 91
Nuclei RISC-V Software Development Kit
most recent commit 5 months ago
K210 Hal ⭐ 63
Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!
most recent commit 3 months ago
Icebreaker Litex Examples ⭐ 57
Example litex Risc-V SOC and some example code projects in multiple languages.
most recent commit a year ago
Riscy Soc ⭐ 54
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
most recent commit 5 years ago
Cep ⭐ 53
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
most recent commit a year ago
Firechip ⭐ 46
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
most recent commit 4 years ago
Neorv32 Setups ⭐ 44
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
most recent commit 3 months ago
Kronos ⭐ 39
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
most recent commit a year ago
Axi Crossbar ⭐ 38
An AXI4 crossbar implementation in SystemVerilog
most recent commit a year ago
Website ⭐ 36
website of hellollvm.org
most recent commit 4 months ago
Hf Risc ⭐ 27
HF-RISC SoC
most recent commit 5 months ago
Popular Hardware Categories
Arduino
Raspberry Pi
Camera
Sensor
Gpu
Firmware
Usb
Keyboard
Cpu
Arm
Categories
Privacy | About | Terms | Follow Us On Twitter

Downloads, Dependent Repos, Dependent Packages, Total Releases, Latest Releases data powered by Libraries.io.

Copyright 2018-2024 Awesome Open Source.  All rights reserved.