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The Top 23 Rtl Risc V Open Source Projects

Open source projects categorized as Rtl Risc V
Categories > Hardware > Risc V
Rocket Chip ⭐ 2,988
Rocket Chip Generator
total releases 9most recent commit 16 days ago
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
Riscv Boom ⭐ 1,524
SonicBOOM: The Berkeley Out-of-Order Machine
most recent commit 3 months ago
Chipyard ⭐ 1,393
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
most recent commit 21 days ago
Firesim ⭐ 778
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
most recent commit 3 months ago
Cores Veer Eh1 ⭐ 770
VeeR EH1 core
most recent commit a year ago
Scr1 ⭐ 688
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
most recent commit 7 months ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Riscv Mini ⭐ 427
Simple RISC-V 3-stage Pipeline in Chisel
most recent commit 7 months ago
Core V Verif ⭐ 359
Functional verification project for the CORE-V family of RISC-V cores.
most recent commit 3 months ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Cores Veer El2 ⭐ 222
VeeR EL2 Core
most recent commit 10 days ago
Dana ⭐ 147
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
most recent commit 4 years ago
Saxonsoc ⭐ 133
SoC based on VexRiscv and ICE40 UP5K
most recent commit 4 months ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Imperas Riscv Tests ⭐ 123
most recent commit 6 months ago
Srv32 ⭐ 109
Simple 3-stage pipeline RISC-V processor
most recent commit 4 months ago
Lm Riscv Dv ⭐ 41
An Open-Source Design and Verification Environment for RISC-V
most recent commit 3 years ago
Rfuzz ⭐ 35
rfuzz: coverage-directed fuzzing for RTL research platform
most recent commit 3 years ago
Tree Core Cpu ⭐ 29
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.
most recent commit 5 months ago
Proteus ⭐ 27
The SpinalHDL design of the Proteus core, an extensible RISC-V core.
most recent commit 7 months ago
Boom Template ⭐ 23
A template for building new projects/platforms using the BOOM core.
most recent commit 5 years ago
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