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The Top 23 Python Systemverilog Open Source Projects

Open source projects categorized as Python Systemverilog
Categories > Systemverilog
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30most recent commit 19 days agopypi pymtl3} Downloads
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19most recent commit 3 months agopypi hdlConvertor} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34most recent commit 4 months agopypi hwt} Downloads
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20most recent commit 2 years ago
Svut ⭐ 59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
total releases 2most recent commit a year ago
Ipxact2systemverilog ⭐ 55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
total releases 24most recent commit 5 months ago
Vim Hdl ⭐ 53
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
most recent commit 4 years ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8most recent commit a year ago
Autosva ⭐ 50
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.
most recent commit 5 months ago
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11most recent commit 5 months agopypi peakrdl} Downloads
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20most recent commit 4 months ago
Cosa ⭐ 35
CoreIR Symbolic Analyzer
dependent packages 1total releases 16most recent commit 3 years agopypi CoSA} Downloads
Shunt ⭐ 29
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
most recent commit 4 months ago
Deepsocflow ⭐ 28
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
most recent commit 4 months ago
Crash_course_for_new_members ⭐ 26
Deep Learning & VLSI Crash Course for New Members
most recent commit 9 months ago
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11most recent commit 6 months agopypi hdlConvertorAst} Downloads
Hwthls ⭐ 20
LLVM based HLS library for HWToolkit (hardware devel. toolkit)
most recent commit a year ago
Autd3 Old Monorepo ⭐ 15
Airborne Ultrasound Tactile Display 3
most recent commit 4 months ago
Fsm2sv ⭐ 13
SystemVerilog FSM generator
most recent commit a year ago
Fpganes_release ⭐ 11
Reconstructing NES game console on Altera DE1-SOC FPGA using System Verilog
most recent commit 7 years ago
Nirah ⭐ 11
Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verification of verilog systems.
most recent commit 5 years ago
Teroshdl Documenter Demo ⭐ 9
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
most recent commit 2 years ago
The 8 Most Depended On Python Systemverilog Open Source Projects
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19latest release July 02, 2021most recent commit 3 months agopypi hdlConvertor} Downloads
Cosa ⭐ 35
CoreIR Symbolic Analyzer
dependent packages 1total releases 16latest release June 03, 2019most recent commit 3 years agopypi CoSA} Downloads
Pysvmodel ⭐ 7
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
dependent packages 1total releases 9latest release August 15, 2023most recent commit 5 months agopypi pySVModel} Downloads
The 10 Latest Releases In Python Systemverilog Open Source Projects
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24latest release December 08, 2023most recent commit 3 months agopypi edalize} Downloads
Ipxact2systemverilog ⭐ 55
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
total releases 24latest release November 26, 2023most recent commit 5 months ago
Pymtl3 ⭐ 344
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
dependent packages 2total releases 30latest release November 02, 2023most recent commit 19 days agopypi pymtl3} Downloads
Peakrdl ⭐ 48
Control and status register code generator toolchain
dependent packages 4total releases 11latest release October 26, 2023most recent commit 5 months agopypi peakrdl} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Peakrdl Regblock ⭐ 36
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
total releases 20latest release October 12, 2023most recent commit 4 months ago
Pysvmodel ⭐ 7
An abstract language model of SystemVerilog (incl. Verilog) written in Python.
dependent packages 1total releases 9latest release August 15, 2023most recent commit 5 months agopypi pySVModel} Downloads
Svut ⭐ 59
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
total releases 2latest release October 27, 2022most recent commit a year ago
Corsair ⭐ 52
Control and Status Register map generator for HDL projects
total releases 8latest release September 26, 2021most recent commit a year ago
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20latest release August 14, 2021most recent commit 2 years ago
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