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The Top 23 Processor Verilog Open Source Projects

Open source projects categorized as Processor Verilog
Categories > Hardware > Processor
Categories > Hardware > Verilog
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
E200_opensource ⭐ 1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
most recent commit 3 years ago
Neorv32 ⭐ 1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
most recent commit 3 months ago
Microwatt ⭐ 634
A tiny Open POWER ISA softcore written in VHDL 2008
most recent commit 3 months ago
Riscv Sodor ⭐ 619
educational microarchitectures for risc-v isa
most recent commit 3 months ago
Openpiton ⭐ 545
The OpenPiton Platform
most recent commit 3 months ago
Zet ⭐ 198
Open source implementation of a x86 processor
most recent commit 6 years ago
Ao486 ⭐ 185
The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.
most recent commit 10 years ago
Ridecore ⭐ 185
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
most recent commit 7 years ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Tinytpu ⭐ 111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
most recent commit 5 years ago
Tang_e203_mini ⭐ 103
LicheeTang 蜂鸟E203 Core
most recent commit 5 years ago
Lm32 ⭐ 72
LatticeMico32 soft processor
most recent commit 10 years ago
Pasc ⭐ 62
Parallel Array of Simple Cores. Multicore processor.
most recent commit 5 years ago
Ao68000 ⭐ 56
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
most recent commit 12 years ago
Tree Core Ide ⭐ 56
The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
most recent commit 2 years ago
Flexpret ⭐ 53
most recent commit 6 months ago
Mips Pipeline Processor ⭐ 52
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
most recent commit 5 years ago
Rj32 ⭐ 42
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
most recent commit 2 years ago
Basic Simd Processor Verilog Tutorial ⭐ 41
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
most recent commit 2 years ago
Mips ⭐ 40
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
most recent commit 6 years ago
Fuxi ⭐ 40
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
most recent commit 3 years ago
Axi Crossbar ⭐ 38
An AXI4 crossbar implementation in SystemVerilog
most recent commit a year ago
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