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The Top 23 Verilog Mips Open Source Projects

Open source projects categorized as Verilog Mips
Categories > Hardware > Mips
Categories > Hardware > Verilog
Mips Cpu ⭐ 356
MIPS CPU implemented in Verilog
most recent commit 7 years ago
Naivemips Hdl ⭐ 63
Naïve MIPS32 SoC implementation
most recent commit 4 years ago
Mips Pipeline Processor ⭐ 52
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
most recent commit 5 years ago
Ddlm ⭐ 42
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
most recent commit 7 months ago
Mips ⭐ 40
A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cache.
most recent commit 6 years ago
Bit_nscscc_suggestion ⭐ 38
为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
most recent commit 3 years ago
Cpu32 ⭐ 26
Tiny MIPS for Terasic DE0
most recent commit 10 years ago
Mips Cpu ⭐ 25
💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
most recent commit 4 years ago
Yari ⭐ 24
YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includes a complete SoC, simulator, GDB stub, scripts, and various examples.
most recent commit 5 years ago
Diy_openmips ⭐ 24
實作《自己動手寫CPU》書上的程式碼
most recent commit 6 years ago
Tinycpu ⭐ 21
Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.
most recent commit 12 years ago
Mips Verilog ⭐ 21
MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.
most recent commit 6 years ago
Buaa_co ⭐ 18
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
most recent commit 5 years ago
Mips ⭐ 14
Mips处理器仿真设计
most recent commit 8 years ago
Coexperiment_repo ⭐ 13
计算机组成原理实验 NUAA Spring 2017
most recent commit 7 years ago
Cpu ⭐ 12
CS3339 Computer Architecture class project - 5 stage MIPS-like processor with forwarding, hazard control, no exception handling.
most recent commit 6 years ago
Mips Cpu ⭐ 11
The Verilog implementation of five-stage-pipelined MIPS CPU (Classic RISC pipeline)
most recent commit 3 years ago
Simple_mips_cpu ⭐ 11
A simple MIPS CPU, for fun.
most recent commit 9 years ago
Csf342 Computer Architecture ⭐ 11
MIPS32 Assembly, Sorting Example in MIPS32 Assembly, CS-F342-Computer-Architecture-Lab
most recent commit 7 years ago
Mips Processor ⭐ 10
5-stage pipelined 32-bit MIPS microprocessor in Verilog
most recent commit 4 years ago
Pipelined Mips ⭐ 10
A Verilog implementation of a pipelined MIPS processor
most recent commit 6 years ago
Bitmips_experiments_doc ⭐ 9
most recent commit 4 years ago
Mips Simulator ⭐ 9
💻 A 5-stage pipeline MIPS CPU design in Haskell.
most recent commit 4 years ago
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