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The Top 6 Python Verilog Vhdl Hdl Open Source Projects

Open source projects categorized as Python Verilog Vhdl Hdl
Categories > Hdl
Categories > Hardware > Verilog
Categories > Hardware > Vhdl
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20most recent commit 2 years ago
Symbolator ⭐ 73
HDL symbol generator
total releases 3most recent commit 4 years ago
Xeda ⭐ 30
Cross EDA Abstraction and Automation
total releases 34most recent commit 4 months ago
Hdlgen Chatgpt ⭐ 9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
most recent commit 3 months ago
Pyxhdl ⭐ 6
Python Frontend For VHDL And Verilog
most recent commit a year ago
Legohdl ⭐ 5
An experimental package manager and development tool for Hardware Description Languages (HDL).
most recent commit 2 years ago
The 3 Latest Releases In Python Verilog Vhdl Hdl Open Source Projects
Xeda ⭐ 30
Cross EDA Abstraction and Automation
total releases 34latest release July 26, 2023most recent commit 4 months ago
Hdl_checker ⭐ 136
Repurposing existing HDL tools to help writing better code
total releases 20latest release August 14, 2021most recent commit 2 years ago
Symbolator ⭐ 73
HDL symbol generator
total releases 3latest release October 19, 2017most recent commit 4 years ago
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