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The Top 23 Hardware Systemverilog Open Source Projects

Open source projects categorized as Hardware Systemverilog
Categories > Hardware > Hardware
Categories > Systemverilog
Ibex ⭐ 1,169
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
most recent commit 3 months ago
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Pcileech Fpga ⭐ 525
FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software
most recent commit 3 months ago
Pulpissimo ⭐ 272
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
most recent commit a year ago
Eurorack Pmod ⭐ 137
Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
most recent commit 3 months ago
Rohd Hcl ⭐ 68
A hardware component library developed with ROHD.
most recent commit 3 months ago
Verilog Systemverilog Guide ⭐ 41
Verilog/SystemVerilog Guide
most recent commit 4 months ago
Deep Neural Network Hardware Accelerator ⭐ 40
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
most recent commit 4 years ago
Fpu ⭐ 37
IEEE 754 floating point library in system-verilog and vhdl
most recent commit 6 months ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit 10 months ago
Deepfreeze ⭐ 21
most recent commit 4 years ago
Fpu Sp ⭐ 19
IEEE 754 floating point library in system-verilog and vhdl
most recent commit 5 months ago
Evsoc ⭐ 16
This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.
most recent commit 7 months ago
Fsm2sv ⭐ 13
SystemVerilog FSM generator
most recent commit a year ago
Hardwaremodules ⭐ 13
A collection of portable hardware modules
most recent commit 9 years ago
Osd Hw ⭐ 12
Open SoC Debug Hardware Reference Implementation
most recent commit 5 years ago
Vhdl2verilog ⭐ 12
Hardware Description Language Translator
most recent commit 3 months ago
Digital Hardware Modelling ⭐ 11
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
most recent commit 3 years ago
Verilog2vhdl ⭐ 11
Hardware Description Language Translator
most recent commit 3 months ago
Orbit ⭐ 11
An HDL package manager.
most recent commit 4 months ago
Nexus ⭐ 9
Open source RTL simulation acceleration on commodity hardware
most recent commit a year ago
Fpga Blit ⭐ 9
FPGA implementation of the Blit terminal
most recent commit 4 years ago
Ultra96 Fractal ⭐ 9
Hardware accelerated Julia set explorer running on Ultra96
most recent commit 2 years ago
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