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The Top 23 Verilog Fpga Vivado Open Source Projects

Open source projects categorized as Verilog Fpga Vivado
Categories > Hardware > Fpga
Categories > Hardware > Verilog
Categories > Vivado
Fpga ⭐ 1,103
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
most recent commit 2 years ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Image Processing ⭐ 123
Image Processing Toolbox in Verilog using Basys3 FPGA
most recent commit 7 months ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Tinytpu ⭐ 111
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
most recent commit 5 years ago
Cnn_for_slr ⭐ 79
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
most recent commit 4 months ago
Intfftk ⭐ 56
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
most recent commit a year ago
Fixed Floating Point Adder Multiplier ⭐ 42
16-bit Adder Multiplier hardware on Digilent Basys 3
most recent commit 9 months ago
Custom_part_data_files ⭐ 28
Xilinx PCIe to MIG DDR4 example designs and custom part data files
most recent commit 4 months ago
Fpga_qpsk Modem ⭐ 26
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
most recent commit 5 months ago
Hwac_object_tracker ⭐ 24
FPGA accelerated TinyYOLO v2 object detection neural network
most recent commit 6 years ago
Scoreboard Wtimer ⭐ 23
Objective of this project was to emulate a Basketball scoreboard, with timer and two teams scores. See readme for pic and more details. FPGA design with Vivado.
most recent commit 3 months ago
My Verilog Examples ⭐ 22
A place to keep my synthesizable verilog examples.
most recent commit 10 months ago
Openhbmc ⭐ 21
Open-source high performance AXI4-based HyperRAM memory controller
most recent commit 2 years ago
Virtio ⭐ 18
Virtio implementation in SystemVerilog
most recent commit 6 years ago
Deep Darkfantasy ⭐ 15
Global Dark Mode for ALL apps on ANY platforms.
most recent commit 3 years ago
Sha256hasher ⭐ 15
SHA-256 IP core for ZedBoard (Zynq SoC)
most recent commit 6 years ago
Rules_vivado ⭐ 11
Bazel rules for Xilinx Vivado
most recent commit 2 years ago
Hdlgen Chatgpt ⭐ 9
HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project
most recent commit 3 months ago
Hardware Implementation Of The Canny Edge Detection Algorithm ⭐ 9
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.
most recent commit 5 months ago
Barebonescortexm0 ⭐ 7
Extremely basic CortexM0 SoC based on ARM DesignStart Eval
most recent commit 6 years ago
Applied_digital_logic_exercises_using_fpgas ⭐ 6
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
most recent commit 2 years ago
Mips 32bit ⭐ 5
Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board
most recent commit 2 years ago
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