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The Top 23 Fpga Verilator Open Source Projects

Open source projects categorized as Fpga Verilator
Categories > Hardware > Fpga
Categories > Verilator
Zipcpu ⭐ 1,139
A small, light weight, RISC CPU soft core
most recent commit 3 months ago
Cores Veer Eh1 ⭐ 770
VeeR EH1 core
most recent commit a year ago
Edalize ⭐ 573
An abstraction library for interfacing EDA tools
dependent packages 3total releases 24most recent commit 3 months agopypi edalize} Downloads
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Wbuart32 ⭐ 237
A simple, basic, formally verified UART controller
most recent commit 3 months ago
Cores Veer El2 ⭐ 222
VeeR EL2 Core
most recent commit 14 days ago
Dblclockfft ⭐ 195
A configurable C++ generator of pipelined Verilog FFT cores
most recent commit 3 months ago
Async_fifo ⭐ 173
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
most recent commit a year ago
Autofpga ⭐ 153
A utility for Composing FPGA designs from Peripherals
most recent commit 3 months ago
Vgasim ⭐ 124
A Video display simulator
most recent commit a year ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Sdspi ⭐ 91
SD-Card controller, using a SPI interface that is (optionally) shared
most recent commit 8 months ago
Dpll ⭐ 82
A collection of phase locked loop (PLL) related projects
most recent commit 3 months ago
Openarty ⭐ 77
An Open Source configuration of the Arty platform
most recent commit 4 years ago
Wbscope ⭐ 67
A wishbone controlled scope for FPGA's
most recent commit 3 months ago
Fakepga ⭐ 66
Simulating Verilog designs on a microcontroller
most recent commit a year ago
Interpolation ⭐ 42
Digital Interpolation Techniques Applied to Digital Signal Processing
most recent commit 3 months ago
Wbi2c ⭐ 35
Wishbone controlled I2C controllers
most recent commit 4 months ago
Zbasic ⭐ 35
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
most recent commit a year ago
S6soc ⭐ 24
CMod-S6 SoC
most recent commit 6 years ago
Virtio ⭐ 18
Virtio implementation in SystemVerilog
most recent commit 6 years ago
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