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The Top 16 Fpga Uart Open Source Projects

Open source projects categorized as Fpga Uart
Categories > Hardware > Fpga
Categories > Uart
Basic_verilog ⭐ 1,333
Must-have verilog systemverilog modules
most recent commit 4 months ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Wbuart32 ⭐ 237
A simple, basic, formally verified UART controller
most recent commit 3 months ago
Fpga Application Development And Simulation ⭐ 96
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
most recent commit 9 months ago
Verilog Uart ⭐ 56
3 modules: UART receiver, UART transmitter, UART to AXI4 master. 3个模块：UART接收器、UART发送器、UART转AXI4交互式调试器
most recent commit 7 months ago
Uart For Fpga ⭐ 35
Simple UART controller for FPGA written in VHDL
most recent commit 3 years ago
Fpga Speech Recognition ⭐ 28
Expiremental Speech Recognition System using VHDL & MATLAB.
most recent commit 6 years ago
Uart ⭐ 25
A simple implementation of a UART modem in Verilog.
most recent commit 2 years ago
Core_dbg_bridge ⭐ 12
UART -> AXI Bridge
most recent commit 3 years ago
Alterajtaguart ⭐ 11
Altera JTAG UART wrapper for Bluespec
most recent commit 10 years ago
Vhdl Axis Uart ⭐ 10
UART to AXI Stream interface written in VHDL
most recent commit 2 years ago
Computer System ⭐ 9
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
most recent commit a year ago
Noop Lo ⭐ 9
A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
most recent commit 4 years ago
Riscv ⭐ 8
32-bit soft RISCV processor for FPGA applications
most recent commit 5 months ago
Core_usb_uart ⭐ 7
USB serial device (CDC-ACM)
most recent commit 4 years ago
Tinyuart ⭐ 5
Lightweight UART core in VHDL
most recent commit 2 years ago
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