Awesome Open Source
Search
Programming Languages
Languages
All Categories
Categories
About

The Top 23 Fpga Rtl Open Source Projects

Open source projects categorized as Fpga Rtl
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140most recent commit 3 months ago
Axi ⭐ 834
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
most recent commit 4 months ago
Firesim ⭐ 778
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
most recent commit 3 months ago
Cores Veer Eh1 ⭐ 770
VeeR EH1 core
most recent commit a year ago
Openwifi Hw ⭐ 560
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
most recent commit 4 months ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Nontrivial Mips ⭐ 362
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
most recent commit 4 years ago
Deepfloat ⭐ 333
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
most recent commit 5 years ago
Cores ⭐ 302
Various HDL (Verilog) IP Cores
most recent commit 3 years ago
Esp ⭐ 267
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
most recent commit 4 months ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62most recent commit 3 months ago
Surf ⭐ 259
A huge VHDL library for FPGA development
most recent commit 5 months ago
Bladerf Wiphy ⭐ 255
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
most recent commit 2 years ago
Fpga_readings ⭐ 249
Recipe for FPGA cooking
most recent commit 3 years ago
Verilog ⭐ 243
Repository for basic (and not so basic) Verilog blocks with high re-use potential
most recent commit 6 years ago
Fpga Usb Device ⭐ 241
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个
most recent commit 7 months ago
Cores Veer El2 ⭐ 222
VeeR EL2 Core
most recent commit 11 days ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34most recent commit 4 months agopypi hwt} Downloads
Fpga Ftdi245fifo ⭐ 178
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
most recent commit 7 months ago
Open Register Design Tool ⭐ 169
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
most recent commit 9 months ago
Ez8 ⭐ 160
The Easy 8-bit Processor
most recent commit 10 years ago
The 4 Most Depended On Fpga Rtl Open Source Projects
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140latest release November 01, 2023most recent commit 3 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Sphinxcontrib Hdl Diagrams ⭐ 43
Sphinx Extension which generates various types of diagrams from Verilog code.
dependent packages 1total releases 9latest release September 21, 2023most recent commit 7 months agopypi sphinxcontrib-hdl-diagrams} Downloads
The 8 Latest Releases In Fpga Rtl Open Source Projects
Spinalhdl ⭐ 1,451
Scala based HDL
dependent packages 4total releases 140latest release November 01, 2023most recent commit 3 months ago
Hdlconvertorast ⭐ 25
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
dependent packages 2total releases 11latest release October 23, 2023most recent commit 6 months agopypi hdlConvertorAst} Downloads
Rggen ⭐ 261
Code generation tool for configuration and status registers
total releases 62latest release October 18, 2023most recent commit 3 months ago
Sphinxcontrib Hdl Diagrams ⭐ 43
Sphinx Extension which generates various types of diagrams from Verilog code.
dependent packages 1total releases 9latest release September 21, 2023most recent commit 7 months agopypi sphinxcontrib-hdl-diagrams} Downloads
Jelly ⭐ 44
Original FPGA platform
total releases 6latest release January 15, 2022most recent commit 3 months ago
Hwtlib ⭐ 33
hardware library for hwt (= ipcore repo)
total releases 28latest release July 02, 2021most recent commit 4 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Pycoram ⭐ 42
Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
total releases 5latest release November 06, 2015most recent commit 7 years ago
Popular Hardware Categories
Arduino
Raspberry Pi
Camera
Sensor
Gpu
Firmware
Usb
Keyboard
Cpu
Arm
Categories
Privacy | About | Terms | Follow Us On Twitter

Downloads, Dependent Repos, Dependent Packages, Total Releases, Latest Releases data powered by Libraries.io.

Copyright 2018-2024 Awesome Open Source.  All rights reserved.