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The Top 23 Verilog Fpga Risc V Open Source Projects

Open source projects categorized as Verilog Fpga Risc V
Categories > Hardware > Fpga
Categories > Hardware > Risc V
Categories > Hardware > Verilog
Vexriscv ⭐ 2,135
A FPGA friendly 32 bit RISC-V CPU implementation
most recent commit 4 months ago
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
E200_opensource ⭐ 1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
most recent commit 3 years ago
Neorv32 ⭐ 1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
most recent commit 3 months ago
Serv ⭐ 1,158
SERV - The SErial RISC-V CPU
most recent commit 4 months ago
E203_hbirdv2 ⭐ 741
The Ultra-Low Power RISC-V Core
most recent commit a year ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Kianriscv ⭐ 396
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
most recent commit 4 months ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Fomu Workshop ⭐ 148
Support files for participating in a Fomu workshop
most recent commit a year ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Ice40_ultraplus_examples ⭐ 115
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
most recent commit 2 years ago
Icestation 32 ⭐ 107
Compact FPGA game console
most recent commit 3 years ago
Tang_e203_mini ⭐ 103
LicheeTang 蜂鸟E203 Core
most recent commit 5 years ago
Fpga Rocket Chip ⭐ 79
Wrapper for Rocket-Chip on FPGAs
most recent commit 2 years ago
Yarvi ⭐ 76
Yet Another RISC-V Implementation
most recent commit 3 months ago
Riscy Soc ⭐ 54
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
most recent commit 5 years ago
Cep ⭐ 53
The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
most recent commit a year ago
Engine V ⭐ 49
SoftCPU/SoC engine-V
most recent commit a year ago
Spu32 ⭐ 48
Small Processing Unit 32: A compact RV32I CPU written in Verilog
most recent commit 2 years ago
Airisc_core_complex ⭐ 48
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.
most recent commit a year ago
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