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The Top 23 Cpu Verilog Open Source Projects

Open source projects categorized as Cpu Verilog
Categories > Hardware > Cpu
Categories > Hardware > Verilog
Vexriscv ⭐ 2,135
A FPGA friendly 32 bit RISC-V CPU implementation
most recent commit 4 months ago
Darkriscv ⭐ 1,795
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
most recent commit 5 months ago
E200_opensource ⭐ 1,688
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
most recent commit 3 years ago
Neorv32 ⭐ 1,337
🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
most recent commit 3 months ago
Zipcpu ⭐ 1,139
A small, light weight, RISC CPU soft core
most recent commit 3 months ago
E203_hbirdv2 ⭐ 741
The Ultra-Low Power RISC-V Core
most recent commit a year ago
Riscv_vhdl ⭐ 552
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
most recent commit 4 months ago
Kianriscv ⭐ 396
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
most recent commit 4 months ago
Risc V Single Cycle Cpu ⭐ 380
A RISC-V 32bit single-cycle CPU written in Logisim
most recent commit a year ago
Riscv ⭐ 364
RISC-V CPU Core (RV32IM)
most recent commit 3 years ago
Mips Cpu ⭐ 356
MIPS CPU implemented in Verilog
most recent commit 7 years ago
Biriscv ⭐ 300
32-bit Superscalar RISC-V CPU
most recent commit 3 years ago
Scamp Cpu ⭐ 279
A homebrew 16-bit CPU with a homebrew Unix-like-ish operating system.
most recent commit 4 months ago
Ustc Rvsoc ⭐ 261
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
most recent commit 7 months ago
Warp V ⭐ 220
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
dependent packages 1total releases 3most recent commit 3 months agonpm warpv-configurator-chakra} Downloads
Fpga Chip8 ⭐ 167
CHIP-8 console on FPGA
most recent commit 5 years ago
Tekno Kizil ⭐ 129
KASIRGA - KIZIL Takımı Teknofest 2023 Çip Tasarımı - KIZIL İşlemci Projesi
most recent commit 9 months ago
Toooba ⭐ 126
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
most recent commit 9 months ago
Icestation 32 ⭐ 107
Compact FPGA game console
most recent commit 3 years ago
Schoolmips ⭐ 106
CPU microarchitecture, step by step
most recent commit 4 years ago
Mcpu ⭐ 104
MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD
most recent commit 5 years ago
Dinocpu ⭐ 101
A teaching-focused RISC-V CPU design used at UC Davis
most recent commit a year ago
Oldland Cpu ⭐ 89
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
most recent commit 8 years ago
The 3 Latest Releases In Cpu Verilog Open Source Projects
Pythondata Cpu Rocket ⭐ 10
Python module containing verilog files for rocket cpu (for use with LiteX).
total releases 33latest release May 30, 2022most recent commit 7 months ago
Warp V ⭐ 220
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
dependent packages 1total releases 3latest release August 12, 2021most recent commit 3 months agonpm warpv-configurator-chakra} Downloads
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