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The Top 23 C Plus Plus Verilog Open Source Projects

Open source projects categorized as C Plus Plus Verilog
Categories > Programming Languages > C Plus Plus
Categories > Hardware > Verilog
Iverilog ⭐ 2,521
Icarus Verilog
most recent commit 3 months ago
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8most recent commit 3 months ago
Circt ⭐ 1,431
Circuit IR Compilers and Tools
most recent commit 3 months ago
Silice ⭐ 1,199
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
most recent commit 3 months ago
Openroad ⭐ 1,102
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
most recent commit 3 months ago
Xls ⭐ 1,087
XLS: Accelerated HW Synthesis
most recent commit 3 months ago
Vtr Verilog To Routing ⭐ 925
Verilog to Routing -- Open Source CAD Flow for FPGA Research
most recent commit 3 months ago
Slang ⭐ 505
SystemVerilog compiler and language services
most recent commit 3 months ago
Hal ⭐ 490
HAL – The Hardware Analyzer
most recent commit 3 months ago
Beagle_sdr_gps ⭐ 446
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
most recent commit 3 months ago
Opentimer ⭐ 368
A High-performance Timing Analysis Tool for VLSI Systems
most recent commit a year ago
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19most recent commit 3 months agopypi hdlConvertor} Downloads
Degate ⭐ 212
A modern and open-source cross-platform software for chips reverse engineering.
most recent commit 6 months ago
Dblclockfft ⭐ 195
A configurable C++ generator of pipelined Verilog FFT cores
most recent commit 3 months ago
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34most recent commit 4 months agopypi hwt} Downloads
Autofpga ⭐ 153
A utility for Composing FPGA designs from Peripherals
most recent commit 3 months ago
Degate ⭐ 151
Open source software for chip reverse engineering.
most recent commit 4 years ago
Metron ⭐ 143
A C++ to Verilog translation tool with some basic guarantees that your code will work.
most recent commit 3 months ago
Verilogcreator ⭐ 141
VerilogCreator is a QtCreator based IDE for Verilog 2005
most recent commit 2 years ago
Openfpgaduino ⭐ 135
All open source file and project for OpenFPGAduino project
most recent commit 5 years ago
Logic ⭐ 121
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
most recent commit 4 years ago
Tinygarble ⭐ 113
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
most recent commit 5 months ago
Istyle Verilog Formatter ⭐ 112
Open source implementation of a Verilog formatter
most recent commit 2 years ago
The 4 Most Depended On C Plus Plus Verilog Open Source Projects
Kratos ⭐ 57
:crossed_swords: Debuggable hardware generator
dependent packages 3total releases 63latest release September 08, 2022most recent commit a year agopypi kratos} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8latest release October 04, 2022most recent commit 3 months ago
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19latest release July 02, 2021most recent commit 3 months agopypi hdlConvertor} Downloads
The 4 Latest Releases In C Plus Plus Verilog Open Source Projects
Verilator ⭐ 1,934
Verilator open-source SystemVerilog simulator and lint system
dependent packages 1total releases 8latest release October 04, 2022most recent commit 3 months ago
Kratos ⭐ 57
:crossed_swords: Debuggable hardware generator
dependent packages 3total releases 63latest release September 08, 2022most recent commit a year agopypi kratos} Downloads
Hdlconvertor ⭐ 258
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
dependent packages 1total releases 19latest release July 02, 2021most recent commit 3 months agopypi hdlConvertor} Downloads
Hwt ⭐ 189
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
dependent packages 3total releases 34latest release July 01, 2021most recent commit 4 months agopypi hwt} Downloads
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